Silicon on Insulator

Low-power and high-temperature sensors and MEMS designs based on bulk, SOI and IC compatible materials and processes are presented here. Target markets are in general public sensors for UV, ozone, CO, liquids presence, e.g. in mobile devices. Or in health, sensors for the medical diagnosis (DNA, RNA, bacteria, viruses). Simple, low cost and low consumption devices are required in medical applications. In our laboratory aluminum oxide interdigitated capacitors have been developed and successfully tested on DNA hybridization test on HIV and cancer (TP-53), as well as on bacteria and humidity or condensation (integrated into a wireless breathing monitoring system), all of them showing comparable results to the state of the art using existing standard biological protocols procedures that open new opportunities for Medical Applications. For UV light based detections (UV Diode), that are ready for use, packaging must be customized. Customers are the kits fabricator to integrate our device...

This paper deals with the theoretical analysis of ultra refraction properties of slab photonic crystals. Strong angular dispersions induced by wavelength variations have been experimentally observed near the Γ–M and Γ–K directions around λ = 1320 nm with negative and positive signs, respectively. An interpretation of these phenomena using three-dimensional plane wave method (3D-PWM) and finite-difference time-domain (3D-FDTD) calculations is presented. Equifrequency surfaces are obtained from PWM calculations and group velocities of Bloch waves excited in the patterned medium are predicted as a function of the incident wave wavelength and wavevector orientation. FDTD calculations have been performed to evaluate the influence of the finite size of the structure and to estimate the photonic crystal coupling losses for various configurations. This theoretical approach allows identifying Bloch waves responsible for the observed properties.

Investigation of electrical characteristics of partially-depleted SOI (silicon-on-insulator) and bulk-Si n-MOSFET devices in order to compare their electrical characteristics using Silvaco software was done and presented in this paper. Two specific channel lengths of the device that had been concentrated are 0.5 and 0.35 micron. The comparisons were focused on three main electrical characteristics that are leakage current, threshold voltage and subthreshold voltage. The device structures were constructed using Silvaco-Athena and the characteristics were examined and simulated using Silvaco-Atlas. Results were analyzed and presented to show that the electrical characteristics of fully-depleted SOI devices are better than that of bulk-Si devices. It has also shown that the partially-depleted SOI device is superior in the submicron region.

The pseudo-MOS transistor (Psi-MOSFET characteristics) is a simple and successful technique for the monitoring of silicon-on-insulator (SOI) wafer quality. To characterize modern ultrathin films, a reconsideration and review of Psi-MOSFET physics and models is required. Selected numerical simulations are presented, which shed light on the intriguing features governing Psi-MOSFET characteristics. Updated models accounting for the density of interface states and

We demonstrate and optically characterize silicon-on-insulator based nanophotonic devices fabricated by nanoimprint lithography. In our demonstration, we have realized ordinary and topology-optimized photonic crystal waveguide structures. The topology-optimized structures require lateral pattern definition on a sub 30-nm scale in combination with a deep vertical silicon etch of the order of ~300 nm. The nanoimprint method offers a cost-efficient parallel fabrication process with state-of-the-art replication fidelity, comparable to direct electron beam writing.

The effects of N2 addition on the etch rate of bulk-silicon and silicon-on-insulator (SOI) separation by implantation of oxygen (SIMOX) and zone melting recrystallization (ZMR) samples using CF4 + O2 and SF6 + O2 plasmas; as well as the damage assessment of the SF~ + O2 plasma are reported. In SF~ + 02 plasma, the N2 additive reduces the etch rate of the masking oxide [chemical vapor deposited (CVD)] while significantly increasing the silicon etch rate and, thus, increasing the selectivity by 44-64 %. In CF4 + O2 plasma, the silicon etch rate is increased due to the N2 addition. However, the increase in selectivity is about 16-45%. The etch rate of SOI silicon especially in SF6 + O2 plasma is higher than that of bulk-silicon samples. The higher etch rate of SOI samples appears related to the higher defect density of the SOI silicon. The damage assessment studied through Schottky diode and metal oxide semiconductor (MOS) capacitor samples indicates that SF6 + O1 plasma with N2 additive introduces less damage as compared to without N2 additive. Furthermore, postmetal annealing at 250~ for 15 rain in N2 + H2 ambient improves the characteristics of both Schottky diode and MOS capacitor devices. Thus the addition of N2 improves the etch rate, and selectivity in some cases, and at the same time decreases the damage. Silicon-on-insulator (SOI) material has a great potential for high speed, high voltage, smart power, and sensor applications as well as radiation hard and high temperature applications. ~-3 Recently, it was demonstrated 4 that high gain vertical polysilicon emitter transistors can be made on ZMR-SOI material. To realize integrated circuits using these polysilicon emitter transistors and other devices within insulated tubs, area-efficient shallow or moderately deep trenches are required for electrical isolation. Several isolation techniques 1 such as LOCOS, mesa, and trench structures, have been utilized to isolate individual devices made on SOI material. LOCOS is a simple and well-established process but it does not take full advantage of possible reduction and savings in both silicon and isolation areas. Moreover, LOCOS does not result in the most useful radiation-hard structures since the LOCOS process leaves larger thin film silicon areas unutilized than those of mesa and trench structures. Anisotropic wet etches may be used to create mesa isolation with precise etching time control so as to not overetch the thin silicon film on top of the buried oxide. Trench isolation provides higher packing density, smaller circuit delays, and tolerates larger variation in SOI silicon film thicknesses. Etch rates, selectivity, and the extent of reactive ion etching (RIE) damage may be significantly different for SOI silicon from that of bulk-St, primarily stemming from the differences in the material propertiesY We have undertaken a study to characterize the etch rates of ZMR, SIMOX, and bulk-St in CF4 + O1 and SF~ + O2 plasmas against several process variables as well as to assess the damage of SF6 + O2 plasma with and without N2 additive. Compared with CF4 + O1 plasma, 9 SF6 + O2 plasma has a much larger concentration of atomic fluorine which in turn gives rise to a higher silicon etch rate.l~ A prime goal in this study is to evaluate th_e effect of N~ additive in two different plasma systems studied, namely, CF4 + O2 and SF6 + O2 and to assess the resulting damage from SF6 + O1 plasma. This work is part of our effort to develop an SOI bipolar integrated circuit process. Recently, Premachandran 1~-12 has shown that an addition of 1% N2 into plasma gives rise to a threefold increase in the etch rate of silicon in CF4 + O2 plasma 1~ and a seven fold increase in the atomic fluorine concentration in SF6 + O2 + N2 plasma which in turn enhances the silicon etch rate.l"~ He has postulated that the increase in the atomic fluorine concentration is responsible for the increased etch rate. In reactive ion etching, by the self-bias voltage reactive ions are accelerated and are bombarded on the wafer surface. This ion-enhanced etching process can cause surface charging effects which can limit the control on the etch profiles. 13 Surface charging also can occur if a nonuniform plasma or an unstable plasma is present during etching. ~4 Plasma instability or plasma nonuniformity produces electron and ion currents that do not balance locally and can generate surface charging effects. 1~ Plasma inconsistencies can be caused by poor electrode design, or poor choice of process conditions (e.g. gas mixtures, flow, and pressures). ~4 Though SF6 is a highly electronegative gas for silicon etching , process modifications such as nitrogen addition can modify its damage effects (possibly change the electronega-tivity effects or alter the sheath potential during discharge) and at the same time improve the etch rate and selectivity. C12 is another alternative but it is highly corrosive and environmentally unfriendly. RIE-induced surface charging may affect the semicon-ductor/devices in various ways, ~6 such as a reduction in the minority carrier lifetime, ~6 an increase in junction leakage current, 17 a reduction of Schottky barrier height, 17 and increase in interface density, (Dit) ~8 and creation of lattice damage. ~9 Schottky diodes and MOS capacitors were used as test vehicles to assess the damage due to SF6 + O2 RIE process. Post metal annealing at 250~ in N~ + H2 ambient improved the characteristics of the Schottky diodes and MOS capacitors. We report here our findings related to the effects of N2 additive to the etch rates of Si in CF4 + 02 and SF6 + 02 plasmas as well as damage assessment of SF6 + 02 plasma with and without N2 additive. Attempts to reduce the damage also are reported. The Si etch rates are studied for bulk-Si and Si epi layer of SOI (SIMOX and ZMR) wafers. We found that the use of SF6 + O2 plasma gives rise to higher

Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.

To overcome the limited bandwidth of chip-to-chip and backplane communication channels at multi-Gb/s data-rates, high-speed I/O transceivers employ a combination of DFE in the RX and FFE in the TX, since these equalizers complement each other to provide an effective equalization solution. Using RX-side FFE instead of TX-side FFE can bring important advantages to the transceiver: it obviates any back-channel for coefficient adaptation and improves RX interoperability with different TXs. RX-FFE is also preferable to simple peaking amplifiers, since it enables greater flexibility in setting the pre-cursor and post-cursor coefficients. However, traditional RX-FFEs with analog delay lines are not area efficient and do not support a wide range of data-rates. This paper describes design techniques that enable the realization of a RX with 4-tap FFE and 5-tap DFE, having area and power efficiency comparable to DFE-only RXs.