Silicon Wafer

The effects of solar radiations on physical properties and molecular structures of 200 nm polystyrene nanospheres (PSN) coated on silicon wafer were explored by field emission scanning electron microscope (FESEM) and attenuated total reflectance-Fourier transform infrared (ATR-FTIR) spectrometer. It is revealed the particles shape of PSN changed from spherical to dumbbell-like shape after solar irradiation. Reduction of the PSN size as much as 23.79% after 5 minutes exposure was also observed in PSN particles. We believed that some of the phenyl moieties of polystyrene broke down to facilitate carbon-carbon cross linkage bonds intra- as well as inter-PSN particles and were shown by ATR-FTIR spectrums. These results proven the shrinkage of PSN particles were caused by the change of the molecular structure of the irradiated PSN to be much more dense material.

The new microelectronic products require the silicon (Si) wafer to be thinned to less than 150 µm in thickness. Residual defect on the wafer surface that leads to wafer breakage with a rough surface still be produced by mechanical grinding. Thus, chemical etching method is essentially applied to produce a reliable thin wafer with smooth surface of desired thickness. In this work, we studied the wet chemical etching effect of different HNO 3 concentrations on total thickness and weight loss, etch rate, morphological and structural properties of Si wafer in the mixtures of HNO 3 and HF. The results showed that the total thickness and weight loss increases with the increasing of HNO 3 concentration and etching time. Higher HNO 3 concentration causes higher etch rate, and the etch rate decreases at prolonged etching time. A smoother and clearer homogeneous Si surface image was observed by optical microscope as the etching time and HNO 3 concentration increase. XRD analysis shows that the intensity of etched Si wafer is higher than the pure one, which might indicate the smoother surface formation after etching. The findings of present study can be valuably referred to produce a reliable and desired Si thin wafer which is crucial in integrated circuit fabrication.

In this study, erbia (Er2O3)-doped Bi2O3 ceramics were prepared from sol–gel derived nanocrystalline powders. The morphological properties were investigated by scanning electron microscopy. X-ray diffraction (XRD) analysis was carried out in order to characterize the phase and crystal structure of the powder samples. Temperature dependent electrical properties were determined by thermogravimetry/differential thermal analyzer (TG/DTA) and 4-point probe techniques. The stable fluorite face centered cubic δ-type phase was observed at room temperature from the XRD result, which was supported by the DTA and temperature dependent electrical conductivity measurements. Electrical conductivity results indicate that there is a transition approximately at 650 °C, which can be attributed to an order–disorder transition (ODT). The activation energy values obtained from the Arrhenius approach for heating and cooling process were presented. Two regimes, corresponding to high temperature region (HTR) and low temperature region (LTR), were observed. As a result of morphological changes during the ODT, the electrical conductivity modifies and the activation energies are different for studied sample at HTR and LTR.

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.

Thermal oxidation is a process done to grow a layer of oxide on the surface of a silicon wafer at elevated temperatures to form silicon dioxide. Usually, it en- counters instability in oxide growth and results in variation in the oxide thickness formed.  This leads to downtime of furnace and wafer scrap.  This study focuses on the factors leading to this phenomenon and finding the optimum settings of these factors. The factors that cause instability to oxide thickness were narrowed down to location of wafer in furnace, oxidation time, gas flow rate and temperature. Characterization and optimization were done using Design of Experiments. Full factorial design was implemented using 4 factors and 2 levels, resulting in 16 runs. Data analysis was done using Multiple Regression Analysis in JMP software. Actual versus predicted plot is examined to determine whether the model fit is significant. Adjusted R2 value was obtained at 99.8% or 0.998 indicating that there is very minimal variatio...

The present study was based on assessments of the anti-parasitic activities of the hematophagous (blood feeding) larvae of malaria vector, Anopheles subpictus Grassi, filariasis vector, Culex quinquefasciatus, Say (Diptera: Culicidae), and the larvae of cattle tick Rhipicephalus (Boophilus) microplus, Canestrini (Acari: Ixodidae). The metallic copper nanoparticles (Cu NPs) synthesized by polyol process from copper acetate as precursor and Tween 80 were used as both the medium and the stabilizing reagent. The efficacy of synthesized Cu NPs was tested against the larvae of blood-sucking parasites. UV-vis spectra characterization was performed, and peak was observed at 575 nm, which is the characteristic to the surface plasmon bond of Cu NPs. The strong surface plasmon absorption band observed at 575 nm may be due to the formation of non-oxidized Cu NPs. X-ray diffraction (XRD) spectral data showed concentric rings corresponding to the 26.79 (111), 34.52 (200), and 70.40 (220) reflections. XRD spectrum of the copper nanoparticles exhibited 2θ values corresponding to the copper nanocrystal. No peaks of impurities are observed in XRD data. The scanning electron micrograph (SEM) showed structures of irregular polygonal, cylindrical shape, and the size range was found to be 35–80 nm. The size of the Cu NPs was measured by atomic force microscope (AFM) in non-contact mode. For imaging by AFM, the sample was suspended in acetone and spins coated on a silicon wafer. The line profile image was drawn by the XEI software and the horizontal line at 6 μm on a 2D AFM image. Research has demonstrated that metallic nanoparticles produce toxicity in aquatic organisms that is due largely to effects of particulates as opposed to release of dissolved ions. Copper acetate solution tested against the parasite larvae exposed to varying concentrations and the larval mortality was observed for 24 h. The larval percent mortality observed in synthesized Cu NPs were 36, 49, 75, 93,100; 32, 53, 63, 73, and 100 and 36, 47, 69, 88, 100 at 0.5, 1.0, 2.0, 4.0, and 8.0 mg/L against A. subpictus, C. quinquefasciatus and R. microplus, respectively. The larval percent mortality shown in copper acetate solution were 16, 45, 57, 66 and 100, 37, 58, 83, 87, and 100 and 41, 59, 79, 100, and 100 at 10, 20, 30, 40, and 50 mg/L against A. subpictus, C. quinquefasciatus, and R. microplus, respectively. The maximum efficacy was observed in Cu NPs and copper acetate solution against the larvae of A. subpictus, C. quinquefasciatus, and R. microplus with LC50 and r 2 values of 0.95 and 23.47, 1.01 and 15.24, and 1.06 and 14.14 mg/L with r 2 = 0.766; 0.957 and 0.908; 0.946; and 0.816 and 0.945, respectively. The control (distilled water) showed nil mortality in the concurrent assay. The chi-square value was significant at p ≤ 0.05 level. This is the first report on anti-parasitic activity of the synthesized Cu NPs and copper acetate solution.

Flip chip packaging technology has been utilized more than 40 years ago and it still experiencing an explosives growth. This growth is driven by the need for high performance, high volume, better reliability, smaller size and lower cost of electronic consumer products. Wafer bumping is ...

Flip chip packaging technology has been utilized more than 40 years ago and it still experiencing an explosives growth. This growth is driven by the need for high performance, high volume, better reliability, smaller size and lower cost of electronic consumer products. Wafer bumping is ...

平成６年 修士論文発表梗概 (Master's thesis presentation outline in 1994)
電気電子工学専攻 (Department of Electrical and Electronic Engineering)
氏名：加藤 勇夫 (Isao KATO)
指導教授：高橋 欣弘 (Yoshihiro TAKAHASHI)

現在、シリコンの大規模集積回路は、極微細化による高性能化、高集積化を実現し、既に半導体メモリーの領域においては1千万素子を集積した64メガビットDRAMが実現している。64メガビットDRAMの設計ルールはおよそ0.3μｍであり、さらに将来の1ギガビットDRAMにおいては0.1μｍ設計ルールが予想されている。このような極微細化の時代において、その基盤となるシリコンウェーハはさらに高い完全性が要求されている。

こうしたなか、これらの集積回路に用いられているのがCzochralski(CZ)成長のシリコン単結晶から得られたシリコンウェーハである。CZシリコンウェーハの特徴は、結晶中にリンやボロンなどのドーパント以外に、酸素が10^18cm^-3という高濃度に存在していることである。この酸素は、結晶成長中に石英るつぼから取り込まれるのであるが、この働きは結晶の機械的強度を上げウェーハの反りを抑えたり、また重金属不純物をデバイス活性領域から取り除くためにデバイスプロセスで盛んに使われているイン卜リンシック・ゲッタリングにと、現在のデバイスプロセスにおいてその役割は重要なものとなっている。したがって、CZシリコンウェーハは、現在の集積回路にはなくてはならない材料となっている。
将来迎えるであろう1ギガビッ卜DRAMの時代に際しては、CZシリコンウェーハ中の重金属不純物などの欠陥濃度が10^9cm^-3以下に抑えられなければならないといわれている。こうした状況を背景として、ウェーハ中に存在する微少濃度欠陥を評価することが必要であるとの要請が強まってきている。しかしながら、これまでに市販のCZシリコンウェーハ中の微少濃度欠陥についての報告はされていない。

そこで、本研究ではCZシリコンウェーハ中の微少濃度欠陥を、高感度な測定法を用いて検出及び評価を行うことを試みた。この目的のために、スペクトロスコピックな性質を有し、非常に高感度な測定法である方形波重み関数方式DLTS法を用いて、10^10cm^-3程度の極微少な濃度の欠陥の検出および評価を行った。これからの集積回路の将来を考えると、このような極微少な濃度の欠陥でさえも接合の漏れ電流や酸化膜耐圧などのデバイス特性に与える影響が無視できないような状況になりつつある。このような状況において、ウェーハ中に存在する微少濃度欠陥の評価を行うことは、今後のデバイスの特性や歩留まりの向上において非常に重要なことと考えられる。
本研究で用いたウェーハは、p型5種類、n型7種類の計12種類のCZシリコンウェーハである。試料はウェーハから1cm角にカットしたものを使用した。p型にはMgを、n型にはAuを蒸着しシヨットキ電極とし、また、オーミック電極としてp型にはGaを、n型にはInGaを用いたショットキダイオードを作製した。このオーミック電極を使用することによりウェーハメー力から供給された状態（as-supplied)のウェーハを評価することが可能となった。その後、作製した試料をDLTS法で測定した。その

結果、観測された欠陥には各ウェーハに共通して観測される欠陥と一部のウェーハに観測される欠陥があった。以下に、本研究で得られた結果について示す。

各クェ一ハ共通して観測される欠陥

(1) as-supplied n型CZシリコンウェーハでは、H-C-0複合体(Ec-0.10eV)が観測される。そして、その濃度はおよそ10^11cm^-3オーダーである。また、as-supplied p型CZシリコンウェーハでは観測されなかった。

CZシリコンウェーハ中には元々炭素及び酸素がそれぞれ～10^15cm^-3、～10^18cm^-3と多量に含まれているので、H-C-0複合体はウェーハメーカでの洗浄工程で混入したと考えられる水素によって、C-0複合体が顕在化されたものであると考えれる。

一部のウェーハに観測される欠陥

(1) as-supplied p型CZシリコンウェーハの内には、Fe-B複合体(Ev+0.10eV)がおよそ10^10 ～ 10^11cm^-3程度存在するものがあることがわかった。
(2) as-supplied p型CZシリコンウェーハの内には、Ev+0.42eVに準位をもつ欠陥がおよそ10^12cm^-3を超える高濃度に存在するものがあることがわかった。また、Ev+0.44eVの準位をもつ欠陥がおよそ10^11cm^-3程度存在するものがあることがわかった。

(3) as-supplied n型CZシリコンウェーハの内には、Ec-0.31eVに準位をもつ欠陥及びEc-0.38eVに準位をもつ欠陥が観測されるものがあり、これらの欠陥は酸素濃度が高い試料で観測され、また、以前報告された鉄を故意に添加した実験の結果と似ているため、酸素及び鉄に関係した複合体と推測される。これらの濃度はおよそ2x10^10cm^-3程度である。

(4) as-supplied n型CZシリコンウェーハの内には、Ec-0.38eV ～ Ec-0.49eVに準位をもつ欠陥は、以前報告された鉄を故意に添加した実験の結果と似ているため、鉄に関係した複合体と推測される。これらの濃度はおよそ2x10^10cm^-3程度である。

(1)、(3)、(4)での鉄混入の可能性は、結晶成長中やサーマル・ドナー消去熱処理中が考えられる。しかし、測定を行ったウェーハの多くでは、これらの欠陥は検出感度1～2x10^10cm^-3程度以下であった。

References:
A. Usami and Y. Tokuda, "Semiconductor device process evaluation technology - focusing on lifetime, DLTS evaluation"
S . M. Sze, "Physics of Semiconductor Devices"

A simple and cost-effective approach for texturing crystalline silicon wafers is proposed. The advantage over conventional texturization processes is the fact that no surfactant is added in alkaline etchants. Hydrogen bubbles, regarded as residuals in conventional texturization processes, are utilized in this approach as etch masks on a silicon surface. This is accomplished by placing a metal grid with suitable